Regarding set-reset (SR) latches, why exactly are certain input SR settings deemed to be 'not allowed' such that a pre-latch gate is used to prevent such settings? What would actually happen in
![a) Schematic of a set-reset latch and its truth table. b) Schematic of... | Download Scientific Diagram a) Schematic of a set-reset latch and its truth table. b) Schematic of... | Download Scientific Diagram](https://www.researchgate.net/publication/369401391/figure/fig6/AS:11431281129021959@1679467834370/a-Schematic-of-a-set-reset-latch-and-its-truth-table-b-Schematic-of-the-circuit.png)
a) Schematic of a set-reset latch and its truth table. b) Schematic of... | Download Scientific Diagram
![flipflop - In SR latch when apply a pulse to reset latch how the Q is changed? - Electrical Engineering Stack Exchange flipflop - In SR latch when apply a pulse to reset latch how the Q is changed? - Electrical Engineering Stack Exchange](https://i.stack.imgur.com/nvh5g.png)
flipflop - In SR latch when apply a pulse to reset latch how the Q is changed? - Electrical Engineering Stack Exchange
![Set Reset Latch Visually Explained With Truth Table and Wave Diagram (Into to Digital Logic Part 11) - YouTube Set Reset Latch Visually Explained With Truth Table and Wave Diagram (Into to Digital Logic Part 11) - YouTube](https://i.ytimg.com/vi/A-4rTUMzq40/maxresdefault.jpg)